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19-4567; Rev 0; 4/09
KIT ATION EVALU LE B AVAILA
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
General Description Features
Crystal Oscillator Interface: 25MHz OSC_IN Interface PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz Outputs One LVDS Output at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELA) Six LVDS Outputs at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELB) One LVCMOS Output at 125MHz/156.25MHz (Selectable with FSELB) Low Phase Jitter 0.4psRMS (12kHz to 20MHz) 0.2psRMS (1.875MHz to 20MHz) Excellent PSNR: -64dBc at 156.25MHz with 40mVP-P Supply Noise at 100kHz Operating Temperature Range: 0C to +70C
MAX3627
The MAX3627 is a low-jitter, precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications. Maxim's proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment. The MAX3627 contains seven LVDS outputs and one LVCMOS output. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz.
Applications
Ethernet Networking Equipment
Typical Operating Circuit
+3.3V 5% 0.1F 10.5 0.1F 0.1F
Ordering Information
PART MAX3627CTJ+ TEMP RANGE 0C to +70C PIN-PACKAGE 32 TQFN-EP*
VDDO_SE Q0 125MHz/156MHz/312.5MHz Z0 = 50 100 Q0 Z0 = 50 ASIC
10F VDDA 0.01F
VDD
VDDO_DIFF
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
125MHz/156MHz/312.5MHz Z0 = 50 Q1
Pin Configuration
TOP VIEW
GND Q7 VDDO_SE VDDO_DIFF
100 ASIC
MAX3627 OPEN OSC_IN Q1 Z0 = 50 125MHz/156MHz/312.5MHz Z0 = 50
Q6
Q6
Q5 18
OPEN
OE
Q2
100 Q2 Z0 = 50
ASIC
24 VDD 25 PLL_BP 26
23
22
21
20
19
17 16 15 14 13 OE FSELB Q4 Q4 VDDO_DIFF Q3 Q3 GND
125MHz/156MHz/312.5MHz Z0 = 50 Q3 33pF X_OUT 25MHz (CL = 18pF) X_IN 27pF Q4 VDD PLL_BP Z0 = 50 Q3 Z0 = 50 100 ASIC
VDDA 27 FSELA 28 OSC_IN 29 MAX3627
125MHz/156MHz/312.5MHz Z0 = 50 Q4 100 ASIC
Q5 12 11 10 9 8 Q2
X_IN 30 X_OUT 31 GND 32
+
1 Q0 2 Q0 3 GND 4 Q1 5 Q1 6 VDDO_DIFF
*EP
125MHz/156MHz/312.5MHz Z0 = 50 Q5 100 Q5 Z0 = 50 ASIC
7 Q2
GND, OPEN, OR VDD
FSELA 125MHz/156MHz/312.5MHz Z0 = 50 Q6 100 ASIC
GND, OPEN, OR VDD
FSELB Q6 Z0 = 50
THIN QFN (5mm x 5mm)
ASIC
33 GND Q7
125MHz/156.25MHz Z0 = 50
*EXPOSED PAD CONNECTED TO GROUND.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, PLL_BP, FSELA, FSELB, OE, OSC_IN ...-0.3V to (VDD + 0.3V) Voltage Range at X_IN ..........................................-0.3V to +1.2V Voltage Range at X_OUT .................................-0.3V to (VDD - 0.6V) Continuous Power Dissipation (TA = +70C) 32-Pin TQFN-EP (derate 34.5mW/C above +70C)..2759mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-65C to +160C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)
PARAMETER Power-Supply Current (Note 2) SYMBOL IDD PLL enabled PLL bypassed CONDITIONS MIN TYP 190 175 1.475 0.925 Figure 1 250 400 MAX 256 UNITS mA
LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6) Output High Voltage Output Low Voltage Differential Output Voltage Amplitude Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Clock Output Rise/Fall Time Output Duty-Cycle Distortion LVCMOS/LVTTL OUTPUT (Q7) Output Frequency Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance R OUT VOH VOL tr, t f I OH = -12mA I OL = 12mA 20% to 80% at 125MHz (Note 5) PLL enabled PLL bypassed (Note 4) 0.15 46 45 0.4 50 50 15 2.6 160 VDD 0.4 0.8 54 55 MHz V V ns % tr, t f Shorted together Short to ground (Note 3) 20% to 80%, RL = 100 PLL enabled PLL bypassed (Note 4) 100 48 46 VOH VOL |V OD | V V mV
|V OD | VOS |V OS | 80 105 5 8 200 50 50 1.125
25 1.275 25 140
mV V mV
mA 330 52 54 ps %
2
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+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)
PARAMETER Input-Voltage High Input-Voltage Low Input High Current Input Low Current SYMBOL VIH VIL I IH I IL VIN = VDD VIN = 0 PLL enabled PLL bypassed (Note 7) I IH I IL CIN VIN = VDD VIN = 0 -80 40 50 1.5 625 FSELA = GND Output Frequency with PLL Enabled (Q0) FSELA = VDD FSELA = high-Z FSELB = GND Output Frequency with PLL Enabled (Q1 to Q7) Output Frequency with PLL Disabled Integrated Phase Jitter Power-Supply Noise Rejection (Note 11) Deterministic Jitter Due to Supply Noise (Note 12) Nonharmonic and Subharmonic Spurs RJRMS FSELB = VDD FSELB = high-Z (Note 8) LVDS outputs LVCMOS output 12kHz to 20MHz, PLL_BP = high (Note 9) 12kHz to 20MHz, PLL_BP = high-Z (Note 10) LVDS outputs LVCMOS output LVDS outputs LVCMOS output (Note 13) f f f f f f = = = = = > 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 20 20 0.4 0.4 -64 -49 2.5 18 -70 -115 -124 -126 -130 -143 -149 125 156.25 312.5 125 156.25 312.5 320 160 1.0 psRMS MHz MHz MHz 60 20 1.2 -80 25 320 3.6 80 CONDITIONS MIN 2.0 0 TYP MAX VDD 0.8 80 UNITS V V A A INPUT SPECIFICATIONS (FSELA, FSELB, PLL_BP, OE)
MAX3627
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6) Input Clock Frequency Input Amplitude Range Input High Current Input Low Current Reference Clock Duty Cycle Input Capacitance VCO Center Frequency CLOCK OUTPUT AC SPECIFICATIONS MHz MHz V A A % pF
PSNR
dBc psP-P dBc
LVDS Clock Output SSB Phase Noise at 125MHz (Note 14)
dBc/Hz
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3
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)
PARAMETER SYMBOL f f f f f f = = = = = > 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz CONDITIONS MIN TYP -113 -123 -126 -130 -144 -151 MAX UNITS
LVCMOS Clock Output SSB Phase Noise at 125MHz (Note 14)
dBc/Hz
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:
A series resistor of up to 10.5 is allowed between VDD and VDDA for filtering supply noise when system power-supply tolerance is VDD = 3.3V 5%. See Figure 4. All outputs unloaded. The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It is expected that the LVDS output short to ground condition is short-term only. Measured with OSC_IN input with 50% duty cycle. Measured with a series resistor of 33 to a load capacitance of 3.0pF. See Figure 2. The OSC_IN input can be DC- or AC-coupled. Must be within the absolute maximum rating of VDD + 0.3V. AC characteristics of LVCMOS output (Q7) are only guaranteed up to 160MHz. Measured with 25MHz crystal (with OSC_IN left open). Measured with 25MHz reference clock applied to OSC_IN. Measured with 40mVP-P sinusoidal signal on the supply at 100kHz. For LVDS the output frequency is 156.25MHz; for LVCMOS the output frequency is 125MHz. Measured with a 10.5 resistor between VDD and VDDA. Parameter calculated based on PSNR. Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc. Measured with 25MHz XTAL oscillator.
Qx RL = 100 Qx V VOD
Qx SINGLE-ENDED OUTPUT Qx IVODI
VOH VOS VOL
Qx - Qx VOD = 2IVODI
DIFFERENTIAL OUTPUT
0
P-P
Figure 1. Driver Output Levels
4
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+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
VCC
800 MAX3627 Q7 33 Z0 = 50 3pF 800 0.1F Z0 = 50 50 50 OSCILLOSCOPE
Figure 2. LVCMOS Output Measurement Setup
Typical Operating Characteristics
(Typical values are at VDD = +3.3V, TA = +25C, crystal frequency = 25MHz.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3627 toc01
PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q0)
MAX3627 toc02
PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q7)
-90 -100 -110 -120 -130 -140 -150 -160
MAX3627 toc03
300 275 250 SUPPLY CURRENT (mA) 225 200 175 150 125 100 75 50 25 0 0 10 20 30 40 50 60 PLL_BP = HIGH PLL_BP = LOW
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
-80 NOISE POWER DENSITY (dBc/Hz)
70
0.1
1
10
100
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
AMBIENT TEMPERATURE (C)
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
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5
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
Typical Operating Characteristics (continued)
(Typical values are at VDD = +3.3V, TA = +25C, crystal frequency = 25MHz.)
PHASE NOISE AT 156.25MHz CLOCK FREQUENCY (Q0)
MAX3627 toc04
PHASE NOISE AT 156.25MHz CLOCK FREQUENCY (Q7)
MAX3627 toc05
PHASE NOISE AT 312.5MHz CLOCK FREQUENCY (Q0)
-90 -100 -110 -120 -130 -140 -150 -160
MAX3627 toc06
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 0.1 1 10 100
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
-80 NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
DIFFERENTIAL OUTPUT WAVEFORM AT 125MHz (LVDS OUTPUT)
MAX3627 toc07
DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVDS OUTPUT)
MAX3627 toc08
DIFFERENTIAL OUTPUT WAVEFORM AT 312.5MHz (LVDS OUTPUT)
MAX3627 toc09
100mV/div
100mV/div
100mV/div
1ns/div
1ns/div
500ps/div
OUTPUT WAVEFORM AT 125MHz (CMOS OUTPUT)
MAX3627 toc10
SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY
MAX3627 toc11
SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY
-10 SPUR AMPLITUDE (dBc) -20 -30 -40 -50 -60 -70 VNOISE = 40mVP-P VNOISE = 100mVP-P fC = 125MHz OUTPUT = Q7 VNOISE = 200mVP-P
MAX3627 toc12
MEASURED USING SETUP IN FIGURE 2 SPUR AMPLITUDE (dBc)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
fC = 156.25MHz
0
VNOISE = 200mVP-P
15mV/div
VNOISE = 100mVP-P VNOISE = 40mVP-P 10 100 NOISE FREQUENCY (kHz) 1000
-80 -90 10 100 NOISE FREQUENCY (kHz) 1000
1ns/div
6
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+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
Pin Description
PIN 1 2 3, 9, 24, 32 4 5 6, 12, 19 7 8 10 11 13 14 NAME Q0 Q0 GND Q1 Q1 VDDO_DIFF Q2 Q2 Q3 Q3 Q4 Q4 FSELB FUNCTION LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Supply Ground LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Power Supply for Q0, Q1, Q2, Q3, Q4, Q5, and Q6 Clock Outputs. Connect to +3.3V. LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Three-State LVCMOS/LVTTL Input. Controls the Q1 to Q7 output divider. When connected to logiclow, the output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. For the Q7 LVCMOS output, the output specification is only valid up to 160MHz. LVCMOS/LVTTL Input. Enable/disable control for the Q4, Q5, and Q6 outputs. The OE pin has an internal 75k pullup resistor. When OE is connected to VDD or left open, Q4, Q5, and Q6 are enabled. When OE is connected to GND, Q4, Q5, and Q6 are disabled to reduce power consumption. When disabled, Q4, Q5, and Q6 are high impedance. LVDS, Noninverting Clock Output LVDS, Inverting Clock Output LVDS, Noninverting Clock Output LVDS, Inverting Clock Output Power Supply for Q7 Clock Output. Connect to +3.3V. LVCMOS Clock Output Core Power Supply. Connect to +3.3V. Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z), the PLL locks to the OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and eliminate intermodulation spurs. Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can be connected to VDD through a 10.5 resistor as shown in Figure 4. Three-State LVCMOS/LVTTL Input. Controls the Q0 output divider. When connected to logic-low, the output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input frequency should be 25MHz. When the PLL is in bypass mode (PLL_BP = low), the OSC_IN input frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be disconnected. Crystal Oscillator Input Crystal Oscillator Output Exposed Pad. Connect to GND for proper electrical and thermal performance.
MAX3627
15
16
OE
17 18 20 21 22 23 25
Q5 Q5 Q6 Q6 VDDO_SE Q7 VDD
26
PLL_BP
27
VDDA
28
FSELA
29
OSC_IN
30 31 --
X_IN X_OUT EP
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7
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
VDD VDDA FSELA PLL_BP VDDO_DIFF
PLL_BP LOGIC 125MHz/156.25MHz/ 312.5MHz 0 OSC_IN CMOS 0/OPEN PFD X_IN CRYSTAL OSCILLATOR X_OUT DIVIDE 25 DIVIDER 5, 4, OR 2 0 LVDS BUFFER 1 LVDS BUFFER FILTER VCO DIVIDER 5, 4, OR 2 1/OPEN Q1 Q1 LVDS BUFFER Q0 Q0
Q2 Q2
1/OPEN
LVDS BUFFER
Q3 Q3
LVDS BUFFER
Q4 Q4
MAX3627
LVDS BUFFER
Q5 Q5
LVDS BUFFER
Q6 Q6
LVCMOS BUFFER 125MHz/156.25MHz
Q7
FSELB
OE
VDDO_SE
Figure 3. Functional Diagram
8
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
Detailed Description
The MAX3627 is a frequency generator designed to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, LVCMOS output buffer, and LVDS output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. The outputs can be switched among 125MHz, 156.25MHz, and 312.5MHz.
LVCMOS Driver
LVCMOS output Q7 is provided on the MAX3627. It is designed to drive single-ended high-impedance loads. The output specifications are only valid up to 160MHz.
MAX3627
Applications Information
Power-Supply Filtering
The MAX3627 is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply pin, VDDA, for the VCO circuitry. The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. Figure 4 illustrates the recommended power-supply filter network for VDDA. This network requires that the power supply is +3.3V 5%. Decoupling capacitors should be used on all other supply pins and placed as close as possible to the pins for best performance.
Crystal Oscillator
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. The crystal frequency is 25MHz. See the Applications Information section for more information.
OSC_IN Buffer
The LVCMOS OSC_IN buffer is internally biased to allow AC- or DC-coupling. This input is internally ACcoupled, and is designed to operate at 25MHz when the PLL is enabled (PLL_BP is left open). When the PLL is bypassed (PLL_BP is set low), the OSC_IN buffer can be operated from 20MHz to 320MHz.
Crystal Input Layout and Frequency Stability
The MAX3627 features an integrated on-chip crystal oscillator to minimize system implementation cost. The integrated crystal oscillator is a Pierce-type that uses the crystal in its parallel resonance mode. It is recommended to use a 25MHz crystal with a load specification of CL = 18pF. See Table 1 for the recommended crystal specifications. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins to minimize the board parasitic capacitance and prevent active signals from coupling into the oscillator.
PLL
The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) that operates at 625MHz. The PLL bandwidth is tuned to 150kHz typical to optimize both phase noise and power-supply noise rejection (PSNR). The VCO output is connected to the PFD input through a feedback divider that divides the VCO frequency by 25 to lock onto the 25MHz reference clock or oscillator. For output Q0, the FSELA pin is used to select among 125MHz, 156.25MHz, and 312.5MHz. For outputs Q1 to Q6, the FSELB pin is used to select among 125MHz, 156.25MHz, and 312.5MHz. For the Q7 output, the FSELB pin is used to select between 125MHz and 156.25MHz. To minimize the jitter induced by power-supply noise, the VCO supply (VDDA) is isolated from the core logic and output buffer supplies.
+3.3V 5% VDD 0.1F MAX3627 VDDA 0.01F 10F 10.5
LVDS Drivers
The high-frequency outputs--Q0, Q1, Q2, Q3, Q4, Q5, and Q6--are differential LVDS buffers designed to drive 100.
Figure 4. Analog Supply Filtering
_______________________________________________________________________________________
9
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3627
Table 1. Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL f OSC CO CL RS 18 50 300 W MIN TYP 25 7.0 MAX UNITS MHz pF pF
The layout shown in Figure 5 gives approximately 2pF of trace plus footprint capacitance per side of the crystal (Y1). The dielectric material is FR4, and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C45 = 27pF and C46 = 33pF, the measured output frequency accuracy is -1ppm at +25C ambient temperature.
Crystal Selection
The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 6 for external capacitance connection.
27pF X_IN CRYSTAL (CL = 18pF) X_OUT 33pF MAX3627
Figure 6. Crystal, Capacitors Connection
Figure 5. Crystal Layout
10
______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs
Interface Models
Figures 7, 8, and 9 show examples of interface models.
VDD 1.4V 180k OSC_IN
Layout Considerations
The inputs and outputs are the most critical paths for the MAX3627 and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3627: * An uninterrupted ground plane should be positioned beneath the clock outputs. The ground plane under the crystal should be removed to minimize capacitance. * Ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3627 and the receive devices. * Supply decoupling capacitors should be placed close to the supply pins, preferably on the same layer as the MAX3627. * Take care to isolate crystal input traces from the MAX3627 outputs. * The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins.
MAX3627
ESD STRUCTURES
Figure 7. Simplified OSC_IN Pin Circuit Schematic
VDDO_SE
10 Q7 10
ESD STRUCTURES
* Maintain 100 differential (or 50 single-ended) transmission line impedance into and out of the part. * Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3627 evaluation kit for more information.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is thermal and electrical ground on the MAX3627 and must be soldered to the circuit board ground for proper electrical performance.
Figure 8. Simplified LVCMOS Output Circuit Schematic
VDDO_DIFF VDD 75k OE
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
ESD STRUCTURES
PACKAGE TYPE 32 TQFN-EP
PACKAGE CODE T3255+5
DOCUMENT NO. 21-0140
Figure 9. Simplified OE Pin Circuit Schematic
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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